1. Field of the Invention
The present invention relates generally to an LSI (Large-Scale Integrated circuit) and more particularly to a semiconductor IC (Integrated Circuit) including a capacitor for a power supply circuit that prevents supply voltage from fluctuating in dependent upon inside loads. The present invention also relates to a method of automatically designing such a semiconductor IC, more specifically the layout of circuit devices, especially capacitors, to be integrated on the basis of unit cells constituting circuit regions.
2. Description of the Background Art
Generally, a semiconductor device has thereinside a power supply circuit and a utility circuit operable with a voltage fed from the power supply circuit for processing signals. The utility circuit is, e.g., a circuit that produces a desired signal from a signal input from the outside. The power supply circuit is expected to apply a stable power supply voltage to the utility circuit. In practice, however, the power supply voltage output from the power supply circuit varies dependently upon the loads of the utility circuit.
It is a common practice with a semiconductor device to insert a capacitor between a power supply line and ground in order to reduce the variation of the power supply voltage. In a semiconductor device, parts constituting a power supply circuit, a utility circuit and a capacitor are laid out with consideration given to the characteristics of the individual parts. Some prior art layouts of a semiconductor device will be described hereinafter.
Japanese patent laid-open publication No. 2000-277618 proposes an LSI arranging method for a standard cell type of LSI design. To sufficiently reduce power supply noise for the stabilization of a power supply, the LSI arranging method disclosed by the publication uses a power supply capacitance cell as one of the standard cells. The capacitance of the power supply capacitance cell is selected in accordance with the drive load capacitance of logic gate cells, which are other standard cells. The power supply capacitance cell is positioned in the vicinity of the logic gate cells.
Japanese patent laid-open publication No. 2000-68476 discloses a semiconductor device including a cell region where logic gate cells are placed and a wiring region where wirings are arranged for connecting the logic gate cells. A capacitance cell is formed at the same level as the logic gate cells in a direction perpendicular to a substrate, and connected to a power supply line. The capacitance cell is automatically placed in the idle portion of the cell region and automatically routed to the other cells that constitute the logic gate cells. This configuration removes the step of laying out level-stabilizing capacitance on a semiconductor device, thereby reducing the total number of fabrication steps.
Japanese patent No. 2682397 teaches a semiconductor IC device which is cell-base designed to obviate an extra space exclusive for a bypass capacitor which would otherwise be required ascribable to the limited capacitance available with each cell, thereby preventing a chip size from increasing to enhance the resistance to noise of an LSI. For this purpose, basic cell, capacitive devices include a group of first MISFETs (Metal-Insulator Semiconductor Field-Effect Transistors) and a group of second MISFETs different in planar shape from the first MISFETs. Capacitive devices are formed between the gate electrodes of the second group of MISFETs and a first and a second power supply voltage feed line. The basic cell, capacitive devices are arranged between function blocks or between block cells.
Japanese patent laid-open publication No. 2000-58751 discloses a semiconductor IC configured to implement stabler synchronization matching with operational frequency, which is increasing today and synchronous to a clock signal. For this purpose, the semiconductor IC includes a first and a second power supply wiring, and a capacitance and a clock driver that are positioned immediately beneath and connected to both of the power supply wirings. The clock driver obviates, in the vicinity of the capacitance, the variation of a power supply voltage ascribable to the charge and discharge of the above capacitance.
Japanese patent laid-open publication No. 106521/1995 proposes a cell-base designed, semiconductor ID device including an n-channel MOS (Metal-Oxide Semiconductor) transistor and a p-channel MOS transistor. The n-channel MOS transistor has a source electrode connected to ground while the p-channel MOS transistor has a gate electrode and a source electrode connected to ground and a power supply, respectively. The two MOS transistors form a capacitor cell for reducing noise ascribable to the operation of an LSI logic circuit.
As for a master slice type of semiconductor IC, Japanese patent laid-open publication No. 61437/1986 teaches that a basic cell positioned in the device region of a semiconductor substrate, but not used for utility, is used as a capacitor. The capacitor is connected between a power supply and ground for absorbing power supply noise, contributing to the stabilization of the device.
The prior art configurations described above use MOS capacitance devices without exception. Although capacitors implemented by MOS capacitance devices are thin and attain a great capacitance, they are apt to interfere with circuits adjoining them. The interference may be reduced if the region forming MOS capacitance is reduced in size or if an exclusive anti-interference region is formed. However, the size reduction of the region forming MOS capacitance blocks a desired capacitance from being attained while the anti-interference region increases the total chip area.
Further, the p-channel and n-channel MOS transistors are formed over the potential wells or on a substrate independently of each other. Such two types of MOS transistors may be formed in group and side by side to function as MOS capacitance devices for various circuits, but cannot be configured to straddle across each other. More specifically, even when the two types of transistors are thus mounted together, only one type of MOS capacitance devices can be used when functioning as capacitance in the active state thereof. It will therefore be seen that MOS capacitance devices lower the mounting efficiency of capacitors in a semiconductor circuit.
It is an object of the present invention to provide a semiconductor IC with mounting efficiency increased and stabler power supply insured, and an automatic designing method therefor.
In accordance with the present invention, a semiconductor IC includes a power supply circuit for feeding a voltage to a utility circuit, and a stablizing circuit for stabilizing the voltage to be applied from the power supply circuit to the utility circuit. The stabilizing circuit includes a first and second electrode. The IC has regions divided into a plurality of blocks each constituting a standard cell. A first electrode is formed in the wiring region for wiring the connections of circuit devices in a standard cell that forms the utility circuit, but formed in a layer different from a layer in which the wiring is formed. A second electrode is formed in a layer different from the layer of the wiring and the layer of the first electrode. Either of the first and second electrodes is connected to a power supply while the other is connected to ground. The first and second electrodes at least partly overlap each other in a direction normal to a plane containing them, thereby forming a capacitance between the layer of the first electrode and the layer of the second electrode.
Also, in accordance with the present invention, a method of automatically designing an IC including a power supply circuit for feeding a voltage to a utility circuit and a stabilizing circuit for stabilizing the voltage begins with the step of dividing the IC into a plurality of block regions, and subdividing each block region into subregions each being implemented as a standard cell. The unit subregions are classified into a subregion for the utility circuit and a subregion for wiring necessary for the utility circuit. The number of standard cells is determined which adjoin each other in an idle subregion not classified in the step of classifying. If the number of standard cells in the idle subregion is greater than a preselected number, the standard cells are coupled and each of a first and a second electrode is formed in a particular layer in the idle subregion. The first and second electrode least partly overlap each other in a direction normal to a plane containing them, thereby forming a capacitance between the layers of the first and second electrodes.